Dynamic Reconfigurable Architectures and Transparent Optimization Techniques presents a detailed study on new techniques to cope with the aforementioned limitations. Finally, works that combine both reconfigurable systems and dynamic techniques are discussed and a quantitative analysis of one them, the DIM architecture, is presented.

As Moore’s law is losing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power dissipation in general purpose processors. At the same time, embedded systems are concentrating several heterogeneous applications in a single device, and hence new architectural alternatives are necessary. Reconfigurable computing has already shown to be a potential solution when it comes to accelerate specific code with a small power budget, but significant speedups are achieved only in very dedicated dataflow oriented software, without capturing the reality of nowadays complex heterogeneous systems. Moreover, any architecture solution should be able to execute legacy code, since there is already a large base of applications and standards. Dynamic Reconfigurable Architectures and Transparent Optimization Techniques presents a detailed study on new techniques to cope with the aforementioned limitations. First, characteristics of reconfigurablesystems are discussed in details, and a large number of case studies is shown. Then, a detailed analysis of several benchmarks demonstrates that such architectures need to attack a diverse range of applications with very different behaviours, besides supporting code compatibility. This requires the use of dynamic optimization techniques, such as Binary Translation and Trace reuse. Finally, works that combine both reconfigurable systems and dynamic techniques are discussed and a quantitative analysis of one them, the DIM architecture, is presented.

Provides a clear review of static and dynamic architecture optimization strategies in the field of reconfigurable computing Shows the importance of dynamic mechanism to accelerate heterogeneous code Demonstrates how different dynamic techniques can be combined in a single architecture that can accelerate heterogeneous code Includes supplementary material: sn.pub/extras

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